The present invention relates to a method for the manufature of integrated electronic devices, in particular high voltage P-channel MOS transistors, and specifically for the manufacture of integrated circuits comprising a MOS transistor of the above specified type and another device having an N.sup.+ region in the epitaxial layer, such as, e.g., NPN and PNP bipolar transistors, P-channel and N-channel MOS and D-MOS transistors or integrated resistors provided in N.sup.+ regions.
Currently, in order to manufacture integrated circuits comprising at least one high voltage P-channel MOS transistor and another device of the specified type, a series of phases is provided to obtain at least the drain extension region of the P-channel MOS and of the N.sup.+ regions of the same MOS and of the associated device. In practice, in the prior art devices, the surface is masked to allow a boron implant only at the main surface area of the device in which the drain extensions will be provided, and then again masked to perform a phosphorus implant to provide the N.sup.+ regions. A subsequent thermal treatment causes diffusion of the boron and respectively of the phosphorus in the related regions as well as oxidation of the device surface.
Such a method, though currently in widespread use, is expensive because of the need to produce two different masks to obtain, respectively, the drain extension region and the additional N.sup.+ regions.